1. Field of the Invention
The present invention relates to the technical field of data processing and, more particularly, to a processor-based automatic alignment device and method for data movement.
2. Description of Related Art
For data processing, data alignment is concerned about the performances of key operations, such as string, array and the like. Upon this problem, U.S. Pat. No. 4,814,976 granted to Hansen, et al. for a “RISC computer with unaligned reference handling and method for the same” performs the alignment as loading or storing unaligned data and reads or writes the data completely by two times as it exceeds the boundary. However, such a processing not only wastes data bandwidth and affects the performance of processor but also causes long codes and wastes storage space. For example, in case of moving three words of data ‘ABCDEFGHIJKL’ starting with address (100+x)h in memory into positions starting with address (200+y)h in memory, where x, y=0, 1, 2 or 3, the required codes are shown in FIG. 1. FIGS. 2-5 respectively illustrate data source and destination addresses that are aligned or unaligned. FIG. 2 shows unaligned data source addresses and unaligned data destination addresses. FIG. 3 shows aligned data source addresses and unaligned data destination addresses. As shown in FIG. 3, when both instructions LWL rA, (100)h and LWR rA, (100+3)h fetch a word at memory address 100h and write it to register rA, it causes resource waste because same operations are performed. FIG. 4 shows unaligned data source addresses and aligned data destination addresses. As shown in FIG. 4, both instructions SWL rA, (200)h and SWR rA, (200+3)h write a value ABCD in the register rA to a word at memory address 200h, which also causes resource waste.
FIG. 5 shows aligned data source addresses and aligned data destination addresses. As shown in FIG. 5, both instructions LWL rA, (100)h and LWR rA, (100+3)h fetch a word at memory address 100h and write it into the register rA, and both instructions SWL rA, (200)h and SWR rA, (200+3)h write a value ABCD in the register rA to a word at memory address 200h, which repeats data read/write and thus severely affect performance.
As cited, if a required length of unaligned data to be loaded is n words, 4n instructions are used to describe read/write (move) operation. Also, at least 4n instruction cycles are used to complete the operation. Since repeated read/write is performed on a same memory position and a same register, processor pipeline is possibly stalled and bus bandwidth is wasted. Especially to some systems without cache, obvious delay can be caused. Therefore, it is desirable to provide an improved method and device to mitigate and/or obviate the aforementioned problems.